1. Field of the Invention
The present invention relates to controllers used with hard disk drive systems used with computers, and more particularly to posted write operations of the controller.
2. Description of the Related Art
Personal computers have been getting ever faster and more powerful at a rapid rate. Significant portions of this advance are due to the increased speeds and data widths of the microprocessors currently available. Microprocessors have gone from 8 bit data widths and operating frequencies of 1 MHz to 32 bit data widths and basic clock rates of 33 MHz. Memory techniques have been developed to, in the greatest part, allow memory system speeds to keep up with the speed of the microprocessor. However, the same speed increases are not true for the various input/output and mass storage systems. The various peripheral devices are often now seen as limitations to the actual speed of a given computer system. If for instance, the personal computer is utilized primarily for word processing applications, then higher disk performance is more important then processor speed in most cases and relative increase in the disk subsystem performance will be much more directly perceived then a given increase in the microprocessor capabilities.
In the past few years, a new type of mass data storage subsystem has emerged for improving the data transfer performance. This subsystem is generally known as a disk array subsystem. One reason for wanting to build a disk array subsystem is to create a logical device that has a very high data transfer rate. This may be accomplished by ganging multiple standard disk drives together and transferring data to or from these drives to the system memory. If n drives are ganged together, then the effective data transferred rate is increased in an amount slightly less than n times. This technique, called "striping," originated in the supercomputing environment where a transfer of large amounts of data to and from secondary storage is a frequent requirement. With this approach, the n physical drives become a single logical devices and may be implemented either through software or hardware.
A number of reference articles on the design of disk arrays have been published in recent years. These include "Some Design Issues of Disk Arrays" by Spencer Ng April, 1989 IEEE; "Disk Array Systems" by Wes E. Meador, April, 1989 IEEE; and "A Case for Redundant Arrays of Inexpensive Disks (RAD)" by D. Patterson, G. Gibson and R. Catts, Report No. UCB/CSD 87/391, December, 1987, Computer Science Division, University of California, Berkeley, Calif.
In general these previous techniques have used several controller boards which could access multiple drives over a small computer system interface (SCSI). Multiple SCSI controller boards were used, with multiple drives connected to each controller board. Software resident in the host computer itself performed the operation of data distribution and control of the various controller boards and of the specific drives on a given controller board. The host computer was also required to do various parity operations required as preferred in the techniques to reduce the amount of space related to error correction versus actual data storage. Thus, while high disk transfer rates could be developed, the host computer was still tied up performing various control functions.
Recent personal computers have developed bus architectures which are capable of sustaining devices which are called "bus masters." A bus master may take control of the computer system at certain times and transfer data between the bus master and the system memory without requiring the service of the main or host processor. The bus master can then release the bus back to the host processor when the transfers are not necessary. In this manner coprocessing tasks can be developed. Especially suitable for such coprocessing tasks are graphical displays, network interfacing and hard disk subsystem control. The various buses or architectures are exemplified by the Micro Channel Architecture (MCA) developed by International Business Machines Corporation (IBM) or the Extended Industry Standard Architecture (EISA). A copy of the EISA specification, provided as Appendix 1 to U.S. Pat. No. 5,101,492, which is hereby incorporated by reference, explains the requirements of an EISA system. Thus it became obvious to place a local processor on a separate board which could be inserted into these busses for disk coprocessing functions. However, it then became critical, particularly when combined with the disk arrays, to allow optimal data transfer capabilities without otherwise slowing down the various devices and capabilities.
To this end Compaq Computer Corporation developed a disk array controller with improved parity development. The disk array controller was incorporated in a product referred to as the Intelligent Drive Array or IDA, which was sold in or about December, 1989 and thereafter. The system operated as a bus master in a personal computer. To this end there was a local processor to handle and control operations in the disk array controller. The local processor interfaced with a bus master controller and with a data transfer controller. The data transfer controller also interfaced with the bus master controller. The bus master controller was used to provide disk subsystem access to the host computer system for transferring disk commands and data.
A second avenue of obtaining and returning data and commands to the host system was through a compatibility controller. The compatibility controller was also linked to the transfer controller. Additionally, up to 8 individual hard disk drives, which have integrated device controllers, were linked to the transfer controller. Finally, an amount of transfer buffer memory was coupled to the transfer controller.
The transfer controller operated as a direct memory access (DMA) controller having four main channels. The main channels were connected to the bus master controller the local processor, the compatibility controller and a disk interface controller. The disk channel was broken down into four subchannels. One of the disk subchannels included an XOR subsystem to allow efficient development of the parity information preferably used for data protection. The data which was transferred between the host system and the disk array was contained in the buffer RAM and was shuttled to and from the buffer RAM by the transfer controller under control of the local processor and the bus master controller. By properly organizing the transfers parity data could be rapidly obtained.
Eventually the need for even higher throughputs then that provided by the IDA was needed as applications grew larger and local area networks (LANs) became larger, the IDA being primarily used in a file server on the LAN.
One technique for improving system performance was the use of disk caching programs. An amount of main memory was utilized as a cache for disk data. Because the main memory was significantly faster than the disk drive, if the desired data was present in the cache, greatly improved performance resulted. In fact, this is a major feature used on the file server when running network operating systems. While disk caching can be readily applied to read operations, it is significantly more difficult to utilize with write operations. A technique known as write posting saves the write data in a cache and returns an operation complete indicator before the data is written to the disks. Then, during a less active time the data is actually written to the disk. However, this technique has one major danger, namely the loss of data which the user believes has been written to the disk drive. If the data was in the posted write cache and power was lost, the data was not actually written, even though the user had been informed of a completion. This data loss may not be noticed for a long period and may cause numerous undetected errors.
Therefore this technique, while providing major benefits, is generally considered unacceptable for many uses, such as on the file servers in LANs, where the data loss could be critical. Therefore the technique is not generally used and potential performance increases are lost in an area where even incremental increases were desirable.